Communication systems typically include logic and hardware to transmit data from an originating device to a target device. In particular, communication systems have routing or switching logic to make high-level decisions that select ports, routes, and media for transmitting the data. Communication systems also include links, each having a transmitter, a medium, and a receiver, to transmit the data in response to those high-level decisions. Data is clocked by the transmitter and transmitted to a receiver, e.g., from a router to a hub, computer to computer, or one processor card to another processor card.
Even when transmitting data across a transmission medium without the corresponding clock signals, noise introduced during the data transmission, such as transmitter jitter, channel jitter and data dependent jitter, reduces the sampling window for data. For example, transmitter jitter can result from many sources such as feed through, random jitter, systematic offsets, duty cycle distortion, and power supply noise. Duty cycle distortion, for instance, is caused by non-symmetric positive and negative duty cycles of a data symbol and can show up either as a high frequency correlated jitter or as a phase step. Further, channel jitter can result from phase dispersion, such as inter-symbol interference (ISI). When a long stream of ones, for example a sinusoid of 800 MegaHertz (MHz) and 2.4 GigaHertz (GHz), transitions into a long stream of zeros, for example a sinusoid of 1.6 GHz, differences in the propagation delay between 800 MHz, 1.6 GHz, and 2.4 GHz of the transmission medium can cause phase shifts at each transition point. The phase shifts, phase steps, and reduced duty cycles reduce the perceivable data-sampling window for the receiver.
Parallel transmission of data involves not only these problems but also problems associated with, e.g., noise coupling between channels and varying amounts of delay across the parallel channels for each string of bits. And, as the physical distances and frequencies of the data transmission increase, these problems are accentuated to the point that parallel data transmission is infeasible when considering high-speed, serial data transmissions as alternatives. High-speed, serial data transmissions avoid issues related to the noise coupling between channels and varying amounts of delay across the parallel channels because one bit is sent at a time across the serial data link.
Serializer-Deserializer (SerDes) facilitates high-speed, serial data transmissions in communications systems, converting data received via a parallel bus into a serial format to be transmitted to a target device via a high-speed, serial data transmission. A SerDes chip at the originating device clocks the data originally and converts data from a parallel format to a serial format. Then, a SerDes chip at each intermediate destination typically clocks the data and re-transmits the data to the next destination until the data reaches the target device.
The transmitters and receivers of the links consume varying amounts of power depending upon characteristics of the data transmission and the medium through which the data transmission is routed. For instance, serial links within a large interconnect system such as a super computer may consume 20 to 37% of total power consumption. More specifically, data transmissions at higher data frequencies, with difficult data traffic types or patterns, via long media, and/or via lossy media, require amplifiers and complex, mixed-signal circuitry. The amplifiers and complex, mixed-signal circuitry improve or maximize the sampling window for bits of data in the data transmission to maintain an acceptable bit error rate (BER), i.e., the number of misinterpreted bit values for the data transmission.
One continuous source of power consumption for high-speed, serial data links at the physical layer is the signal-detect function typically incorporated in to the receiver of the SerDes. Receivers are designed to verify that a valid data signal is being received by monitoring incoming data transmissions for logical ones and zeroes. Data signals include, for example, positive voltages for logical ones and negative voltages for logical zeroes, or vice versa. In such circumstances, the receivers verify receipt of a valid data signal by verifying that logical ones and zeros are being received. Receipt of logical ones and zeroes is verified by comparing the data transmission to both a positive reference voltage and a negative reference voltage. If the data transmission includes voltages above the positive reference voltage or below the negative reference voltage during a period of time in which valid data is expected, the receiver confirms receipt of the valid data signal. However, power is continually consumed by a detector for the positive reference voltage and the detector for the negative reference voltage regardless of which detector actually detects bits in the data transmission.
Current attempts to reduce power consumption for the signal-detect function significantly reduce the receivers' ability to accurately detect signal loss at the physical layer. These systems compare data transmissions with a single reference voltage, i.e., either a reference for a logical one or a reference for a logical zero, ignoring the second reference voltage. However, one of the anticipated symptoms for problems associated with high-speed, serial data links, is the inability to produce both types of bits. For example, the link may correctly transmit logical ones while failing to transmit logical zeroes. Such solutions leave detection of problems related to one type of bit to higher layer logic. A further example is that the medium over which the data transmission is communicated, such as a wire for electrical signals, may be, e.g., shorted to the positive or negative rail.
Therefore, there is a need for a scheme to reduce power consumption for the signal-detect function of receivers without significantly reducing the receivers' ability to accurately detect signal loss at the physical layer.